1. Field of the Invention
This invention relates generally to semiconductors and control methods therefor, and more particularly, to a semiconductor device having a non-volatile memory cell array and a control method therefor.
2. Description of the Related Art
In recent years, non-volatile memory semiconductor devices, in which data is rewritable, have been widely used. For instance, in a flash memory that is a typical non-volatile memory, a transistor composing a memory cell has a floating gate or an insulating film, each of which is also known as a charge storage layer. Data is stored by storing the charge in the charge storage layer. When the charge is stored in a trap layer, a threshold voltage of the transistor is changed. Data is read by reading the threshold voltage of the transistor as a drain current value.
There have been developed Silicon Oxide Nitride Oxide Silicon (SONOS) type flash memories in which the charge is stored in the trap layer made of a silicon nitride layer for purposes of higher memory capacity. In addition, among the flash memories, there has been developed a flash memory in which two or more charge storage regions are provided in one transistor in order to increase the memory capacity. An example is disclosed in Japanese Patent Application Publication No. 2000-514946 where two charge storage regions are provided between a gate electrode and a semiconductor substrate of a transistor. This transistor symmetrically operates switching a source and a drain. This realizes a virtual ground architecture in which a source region and a drain region are not distinguished.
FIG. 1 (PRIOR ART) is a view schematically illustrating data reading in a conventional technique. A core cell 12, which is a non-volatile memory cell, is arranged in a non-volatile memory cell array 10. In fact, multiple core cells are arranged. Yet, only one core cell is shown here. The source of the transistor in the core cell 12 is connected to ground, and the drain thereof is connected to a core cell data line 14. The core cell data line 14 is connected by a first current-voltage conversion circuit (cascode circuit) 16. There are also arranged multiple core cell data lines 14 and multiple first current-voltage conversion circuits 16 as a matter of fact. Yet, only one is respectively shown.
In a similar manner, a reference cell 22 is connected to a second current-voltage conversion circuit (cascode circuit) 26 through a reference cell data line 24. An output from the first current-voltage conversion circuit 16 and an output from the second current-voltage conversion circuit 26 are input into a sense amplifier 18, so as to be sensed and output. There are also arranged multiple sense amplifiers 18. Yet, only one sense amplifier is shown here.
Data is read from the core cell 12 in a following manner. Firstly, the first current-voltage conversion circuit 16 pre-charges the core cell data line 14 to set the voltage level of the core cell data line 14 to a given voltage level. Then, current flows through the core cell 12, in accordance with the data written into the core cell 12. The first current-voltage conversion circuit 16 converts the current value into the voltage level to output to the sense amplifier 18.
The threshold voltage of the transistor in the reference cell 22 is a reference threshold voltage that determines whether the data in the core cell 12 is “1” or “0”. In a similar manner as the core cell side, the second current-voltage conversion circuit 26 pre-charges the reference cell data line 24, and converts the current value of the reference cell 22 into the voltage level to output to the sense amplifier 18. The sense amplifier 18 compares the output from the first current-voltage conversion circuit 16 with the output from the second current-voltage conversion circuit 26, and provides an output according to whether the data written into the core cell is “1” or “0”.
Japanese Patent Application Publication No. 2001-250391 discloses a circuit having a current-voltage conversion circuit for core cells and a current-voltage conversion circuit for reference cells, and an output from the current-voltage conversion circuit for the reference cells is input into the current-voltage conversion circuit for the core cells. U.S. Pat. No. 6,259,633 discloses a circuit having a transistor such that a current-conversion circuit speeds up pre-charging.
Depending on the type of the non-volatile memory, data is concurrently read from multiple core cells 12 connected to an identical word line. For example, in a memory device having a memory array architecture of NOR type or virtual ground type and also having an interface identical to a NAND type flash memory, for example, 512 bits are concurrently read out of the core cells connected to an identical word line. This read operation is performed 32 times in a continuous manner, each of such read out data (2 k bytes in total) is memorized in a register, and every 16 bits are output from the register to outside of the chip in a continuous manner. The first current-voltage conversion circuit 16 and the sense amplifier 18 are provided for each core cell data line 14. Accordingly, when data is read out of the core cells 12 concurrently, the output from the second current-voltage conversion circuit 26 is input into each of the sense amplifiers 18. For example, when 512-bit data is concurrently read, 512 sense amplifiers 18 are connected.
Meanwhile, the outputs from the second current-voltage conversion circuit 26 are connected to 512 sense amplifiers 18. As stated, the second current-voltage conversion circuit 26 is connected by such a heavy load that it takes time to pre-charge an output line of the second current-voltage conversion circuit 26. This causes a problem that a data read time gets longer.